1. Field of the Invention
The present invention relates to a control circuit for controlling an operation mode in a pseudo-static RAM, in particular, a chip select standby mode in a pseudo-static RAM.
2. Description of the Related Art
In order to increase the integration density of a static RAM, memory cells are employed as in a dynamic RAM and a counter for refreshing is formed, together with the memory cells, on a common chip as known in the art. By so doing, a pseudo-static RAM (PSRAM) is realized which operates in a manner similar to that of a static RAM.
For PSRAM, write and read modes and CS (chip select) standby mode are known as specific modes. In a PSRAM, the operation mode is determined in accordance with the level of the chip select signal CS at a time when a chip enable signal CE of the PSRAM becomes a "low (L)" level. At the time when the chip enable signal CE becomes a "L" level, for example, a normal write or a normal read mode is involved if the chip select signal CS is a "high (H)" level and a CS standby mode is involved. If the chip select signal CS is a "L" level, at the time when the CE signal becomes a "L" level, a program operation, such as the write operation in a chip, is inhibited.
A control circuit associated with the CS standby mode in a PSRAM is arranged as set out below. A chip enable control circuit generates a group of control signals (.phi.CE, .phi.P1, .phi.P2) in synchronism with the chip enable signal CE. A chip select control circuit latches the chip select signal CS with the group of use of the control signals (.phi.CE, .phi.P1, .phi.P2) and delivers a latched signal .phi.CS as an output signal. A write enable control circuit delivers a write enable signal WE in accordance with the latched signal .phi.CS.
A relation of the operation of these control circuits to their associated signals is as follows.
At a time of normal data write-in operation, a write enable signal .phi.WE of the write enable control circuit is made active and the write series circuit is set in an operable state. With the chip enable signal CE at a "H" level, a normal standby state is involved. With the chip enable signal CE and chip select signal CS both at the "L" levels, the CS standby mode is involved. In a normal standby state and CS standby mode, the write enable signal .phi.WE is controlled by the write enable control circuit to be inactive. At this time, a dissipation current is suppressed to a minimum in the write series circuit.
As a signal for controlling the write enable control circuit, the latch signal .phi.CS is employed which is outputted from the chip select control circuit. The latch signal .phi.CS is delivered as an output signal when and only when the chip select signal CS is latched by the group of control signals (.phi.CE, .phi.P1, .phi.P2) subsequent to the transmission of the group of control signals (.phi.CE, .phi.P1, .phi.P2) to the chip select control circuit. Thus, the latch signal .phi.CS is delivered as an output signal with a considerable delay of time.
If the chip select signal CS is in the "H" level when the chip enable signal CE goes to the "L" level, a write enable signal .phi.WE of the write enable control circuit is made active to obtain a read mode. Since, however, the write enable control circuit is controlled by only the latched signal .phi.CS, the generation of the write enable signal is delayed, causing a marked decrease in the write operation margin.